The present invention relates generally to data bus communications, and more specifically to a system incorporating a high-speed bus and a relatively low-speed peripheral bus.
Although it is tempting to view the history of personal computers (PCs) solely in terms of the evolution of CPUs, a more complete view must take into account the evolution of the buses around which the computers are built. Nowhere is this more notable than in the case of IBM-compatible PCs, which are based on Intel-compatible microprocessors.
In 1981, IBM introduced the 8-bit IBM Personal Computer PC XT, based on the Intel 8088 microprocessor running at 4.77 megahertz (4.77 MHz), a 1-megabyte (1-MB) memory address space, 5.25-inch floppies and a system board with five 8-bit expansion bus slots. IBM adopted an open architecture policy and published the technical specifications of the system bus, electronics, and BIOS. IBM and Microsoft developed the 8-bit operating system called DOS. Many manufacturers were able to offer PCs that operated exactly like the IBM PC. This enabled the development and sale of hundreds of PC models, thousands of application software packages and hundreds of XT bus peripheral boards. The 8-bit XT bus ran at 4.77 MHz and offered a peak data transfer rate of less than 500 kilobytes/sec (500 KB/sec).
In 1984, IBM upgraded the PC by introducing the 16-bit PC AT, based on the Intel 80286 microprocessor with a 16-MB address range. This microprocessor was offered in 6-, 8-, 12- and 16-MHz versions. The system specification were enhanced and although the technical specifications were not released most PC companies were able to figure out the specifications and offer compatible products. The majority of the systems ran the 8-bit DOS operating system. The PC AT offered a 16-bit I/O bus that became known as the AT bus. This bus extended the XT bus by adding an extra connector and signals. The AT bus accepted both the older 8-bit XT bus cards as well as the new 16-bit AT bus cards. This bus later became known as the Industry Standard Architecture or ISA. The 16-bit AT bus ran at 8 MHz and offered a peak data transfer rate of approximately 2 MB/sec.
Since application software vendors compete against each other on the basis of software features, application software became more functional and complex, and required more processor speed and memory addressing capability. Intel responded in 1986 to these demands with the 16-MHz 32-bit 80386 microprocessor. The 32-bit capability enabled a 4-gigabyte (4-GB) memory address space. However, the majority of 386 systems were sold with the 16-bit ISA bus and 8-bit DOS operating system.
In 1987, IBM introduced a completely new PC architecture called the Micro Channel Architecture (MCA), which introduced a new concept to the PC world called bus mastering. A bus master is a special peripheral card that can transfer blocks of data directly to the system memory without CPU intervention. Bus-mastering off-loads the CPU to do other work. Bus-mastering was the first step in bringing multiprocessor technology to the PC. The MCA bus runs at 8 MHz and offers a peak transfer rate of 20 MB/sec.
In the absence of IBM extending the 16-bit ISA bus to 32 bits, many companies employed a two-bus approach--a proprietary 32 bit CPU-to-memory bus with the 16-bit ISA bus for I/O. Comparing offered the "Flex Architecture", AST the "Smart Slot", etc. These 32-bit CPU-to-memory buses were fairly simple and offered nothing more than increased memory bandwidth. Each system was designed to make the memory bus transparent to the operating system software and applications. Eventually, the 32-bit 80386 microprocessor was offered with clock speeds as high as 33 MHz, but the ISA bus remained at 16 bits and 8 MHz, thus becoming a system bottleneck especially in applications with intense disk or graphic activity. Dual bus PCs offered a 32-bit data path to memory matching the width of the CPU but did not address the problem of I/O bottleneck at all. These system were the first "two-bus PCs" where each bus was tuned to different tasks.
In 1988, Compaq and a group of PC vendors offered a 32-bit extension to the 16-bit ISA bus. The EISA bus is a multi-master bus that runs at 8 MHz, offers a peak transfer rate of 33 MB/sec and can accept both EISA and ISA bus cards. Today, the EISA bus is being offered by many PC compatible companies and is becoming more popular as prices decline and bus cards become more available.
As more complex application software migrates to the PC architecture, faster processors incorporating the latest microprocessor architectural concepts are being developed. These high-performance microprocessors require a high bandwidth to main memory and also create a demand for high bandwidth I/O, far in excess of the bandwidth of the EISA or Micro Channel. Additionally, both of these buses are I/O buses and not multiprocessor buses. Architectures that employ multiples of these advanced microprocessors in a multiprocessor configuration require even higher bus bandwidth and special electronics to coordinate the processor activities. An efficient multiprocessor organization is a tightly-coupled, shared-memory architecture where multiple processors can access to a common main memory over a high-speed bus. Each CPU has its own cache memory. In a multiprocessor architecture, a prime concern is keeping the multiple caches synchronized with the most current data. The system bus must provide cache coherehey capabilities so that each processor has an identical view of memory.
Corollary introduced a dual-bus architecture that brought multiprocessor capability and ECC memory to the PC architecture and was the first multiprocessor PC bus to be adopted by several computer companies. Corollary designed a bus that connected multiple CPU caches together which was dubbed the "C-Bus" for "cache" bus. It employs a 32-bit, 16-MHz, 64-MB/sec design and an interrupt scheme to handle multiple processors. This bus also interfaces to the ISA and EISA buses via a special CPU. The C-bus architecture requires this special CPU, called the master, to handle all PC bus system activity. This asymmetry becomes a serious bottleneck as the number of processors increases.